Home » EDA » Cadence Design Flows Now Certified for TSMC s Latest N4P and N3E Processes

TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.

Cadence Design Systems Inc. s digital and custom/analog design flows have been certified to Taiwan Semiconductor Manufacturing Co. Ltd s (TSMC) latest N4P and N3E processes in support of the new Design Rule Manual (DRM) and FINFLEX technology. Through continued collaborations, the companies have also delivered the corresponding N4P and N3E process design kits (PDKs) to accelerate advanced-node mobile, AI and hyperscale computing design innovation. Customers have already started using the latest TSMC process technologies and certified Cadence flows to accomplish optimal power, performance and area (PPA) goals and speed time to market.

The Cadence and TSMC R D teams worked together closely to ensure the digital flow met TSMC’s advanced N4P and N3E certification requirements. Cadence’s complete RTL-to-GDS flow includes the Innovus Implementation System, Quantus Extraction Solution, QuantusFS solution, Tempus Timing Signoff Solution and ECO option, Pegasus Verification System, Liberate Characterization Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution. The Cadence Genus Synthesis Solution and predictive iSpatial technology are also enabled for the TSMC N4P and N3E process technologies.

The digital full flow offers several key capabilities that support the TSMC N4P and N3E process technologies, including native mixed-height cell row optimization from synthesis to signoff engineering change orders (ECOs) for optimal PPA; standard-cell row-based placement; implementation results that are well-correlated to signoff for faster design closure; enhanced via pillar support for better design performance; large libraries containing many multi-height, voltage threshold (VT) and drive-strength cells; timing robustness cell characterization and analysis; reliability modeling using aging-aware STA; and CCSP model enhancements providing improved accuracy and simplified characterization for analysis via the Voltus IC Power Integrity Solution.

10/17-19 EAC